Quote:
Originally Posted by BrianG
Saturating a MOSFET simply means driving the gate with enough voltage that the drain and source has as little resistance as possible. An "ideal" FET would have infinite gate resistance, zero gate capacitance, zero on-resistance, and infinite slew rate. No losses means 100% efficiency.
Anyway, less resistance equates to less voltage drop, which equates to less power wasted as heat on the FET for a given current. However, aside from an FETs rdson value, it takes time (albeit small) from when the FET turns off to fully on, and back again. This is called the slew rate and is measured in volts per second (or milli-second). During that time, there is variable "resistance" (increasing as the FET approaches "off", decreasing as it approaches "on"). Since a PWM signal switches on/off many many times per second, it makes sense that at those times is where you have the majority of the losses. OK you say, so why not simply reduce the on/off cycles? Well, you can, to a degree, but then you have motor inductance and the role it plays with the PWM "A/C" to worry about.
Paralleling enough FETs reduces the total rdson value and also reduces the voltage drop during the on/off cycles. If a FET can be totally saturated AND have a very very fast slew rate, losses are greatly reduces. Then, the FET current rating is pretty much limited by the package wiring.
I hope I explained that for you; I tend to ramble.  |
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