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01.23.2010, 11:39 PM
Yeah, he has some design challenges when trying to test at such low voltages. Might need to pump up the gate drive a bit higher to get a cleaner and "squarer" signal from the FETs. This is one reason why I thought about testing 2s or 3s packs only and using an ESC in brushed mode; the ESC is already done and can handle lots of current (nothing on the order this guy is testing though). The voltage is low enough to keep load power dissipation somewhat reasonable, yet high enough voltage to eliminate the problems this guy is having. Besides, testing very high currents at such low voltages make it imperative that the wire/contact resistance is as close to 0 as possible. A difference of even 0.001 ohms can make a substantial difference.
I also think it is important to test performance in a pack formation since that is how we use cells. It lumps contact and wire resistance together to get a system performance baseline. This guy seems to be more concerned about if the cell itself can handle the abuse without causing collateral damage.
I haven't totally written off this project yet. For instance, I want to ask Patrick on his thoughts about paralleling two MMM ESCs. That will obviously increase the current capability, lower ESC resistance, and reduce the effect of copper losses. Since no back-EMF signal is present/used in brushed mode, I don't see why this won't work as long as both ESCs output the exact same signal at the same time. Ideally, it would be nice if there was a "slave port" on these ESCs so you can control the power section of each with the "brains" of the master ESC. Obviously, doing this increases the cost of the project to the point where it is no longer a relatively cheap "home brew" setup.
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