FETs are "voltage driven" (very high input impedance) as opposed to current-driven transistors, so paralleling them is easy without "loading down" the driver circuit. FETs also have a negative temperature coefficient which means they conduct less the more they heat up, so they are kinda self-regulating in a way.
And parallelling more FETs splits the current load between each as well as reducing the overall Rdson for reduced voltage drop and heat for a given current.
But the more FETs you have, the longer the signal paths become, which may be a problem with noise and/or transient response since we're dealing with capacitive FET gates.
I'm sure Griffin can elaborate much more on this, but I saw he was offline so I thought I'd throw in my $0.02.
